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Semiconductor Trainer
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- Company
- Saffroot Technologies LLP
- Location
- Bengaluru, Chennai, Coimbatore
- Employment type
- Freelance
- Experience
- 3-6
- Salary / budget
- Not specified
- Date posted
- 2026-07-06
- Notice period
- 30 days
- Skills
- Static Timing Analysis, Cadence Innovus, SPICE Simulation Expertise
Role overview
Job description
Category Details Qualification B.E. in Electronics; M.Tech in VLSI Design Experience Experience in CMOS design, low-power optimization, and SPICE simulation using Cadence Virtuoso. Research experience in ML-assisted power and timing optimization. Knowledge Strong foundation in Digital IC Design, Low-Power CMOS Circuits, RTL Design, Static Timing Analysis (STA), Machine Learning for Hardware Security, and Cadence-based Layout Design. Skills EDA Tools: Cadence Virtuoso, Cadence Genus, Cadence Innovus, Xilinx Vivado. Hardware Description Languages: Verilog (RTL), SystemVerilog. Technical Skills: Digital Logic Design, CMOS Design, SPICE Simulation, Low-Power Optimization, RTL Development, STA.