Semiconductor Trainer
Company: Saffroot Technologies LLP
Role summary: Category Details Qualification B.E. in Electronics; M.Tech in VLSI Design Experience Experience in CMOS design, low-power optimization, and SPICE simulation using Cadence Virtuoso. Research experience in ML-assisted power and timing optimization. Knowledge Strong foundation in Digital IC Design, Low-Power CMOS Circuits, RTL Design, Static Timing Analysis (STA), Machine Learning for Hardware Security, and Cadence-based Layout Design. Skills EDA Tools: Cadence Virtuoso, Cadence Genus, Cadence Inno
Location: Bengaluru, Chennai, Coimbatore
Employment type: Freelance
Experience: 3-6
Salary / budget: Not specified
Notice period: 30 days
Skills: [{"name": "Static Timing Analysis", "normalized_key": "static timing analysis", "weight": 0.3, "skill_type": "workflow", "curation_decision": "keep_direct", "assessment_type": "hybrid", "evaluation_confidence": "high", "curation_reason": "Specific and distinct enough to drive direct interview questions.", "quality_score": 0.857, "supporting_lines": ["Strong foundation in Digital IC Design, Low-Pow
Date posted: 2026-07-06
Why this role matters
Category Details Qualification B.E. in Electronics; M.Tech in VLSI Design Experience Experience in CMOS design, low-power optimization, and SPICE simulation using Cadence Virtuoso. Research experience in ML-assisted power and timing optimization. Knowledge Strong foundation in Digital IC Design, Low-Power CMOS Circuits, RTL Design, Static Timing Analysis (STA), Machine Learning for Hardware Security, and Cadence-based Layout Design. Skills EDA Tools: Cadence Virtuoso, Cadence Genus, Cadence Inno
Related job pages
- More Semiconductor Trainer jobs
- More jobs in Bengaluru, Chennai, Coimbatore
- Jobs for 3-6 experience
- More jobs at Saffroot Technologies LLP
- Browse job search hub
Job description
Category Details Qualification B.E. in Electronics; M.Tech in VLSI Design Experience Experience in CMOS design, low-power optimization, and SPICE simulation using Cadence Virtuoso. Research experience in ML-assisted power and timing optimization. Knowledge Strong foundation in Digital IC Design, Low-Power CMOS Circuits, RTL Design, Static Timing Analysis (STA), Machine Learning for Hardware Security, and Cadence-based Layout Design. Skills EDA Tools: Cadence Virtuoso, Cadence Genus, Cadence Innovus, Xilinx Vivado. Hardware Description Languages: Verilog (RTL), SystemVerilog. Technical Skills: Digital Logic Design, CMOS Design, SPICE Simulation, Low-Power Optimization, RTL Development, STA.